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Gabriel Ganzer
Turin, Italy
Gabriel has a bachelor's degree in Computer Engineering from the Federal University of Santa Catarina, Brazil. He has experience with Embedded Systems and Digital Design, focusing on energy efficiency and power optimization. Currently, he is pursuing a master's degree in Computer Engineering from Politecnico di Torino, Italy.
CodersRank Score
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This represents your current experience. It calculates by analyzing your connected repositories. By measuring your skills by your code, we are creating the ranking, so you can know how good are you comparing to another developers and what you have to improve to be better
Information on how to increase score and ranking details you can find in this blog post.
258.1
CodersRank Rank
Top 3%
Top 1
Assembly
Developer
Italy
Top 100
HTML
Developer
Italy
Top 5
MATLAB
Developer
Italy
Highest experience points: 0 points,
0 activities in the last year
Assembly
31.7
exp.
MATLAB
31.4
exp.
HTML
44.9
exp.
Perl
28.9
exp.
JavaScript
24.6
exp.
CSS
24.7
exp.
Shell
12.1
exp.
Batchfile
10.9
exp.
C++
6.2
exp.
Java
5.4
exp.
Python
5
exp.
List your work history, including any contracts or internships
Software/Hardware Integration Lab (LISHA)
Feb 2018 - Jul 2018 (5 months)
Intern, Thesis Project
Researched System-on-Chip (SoC) architectures for embedded systems and routing algorithms. Designed and published a mechanism for packet delivery measurement in a Network-on-Chip (NoC) used to interconnect processing units running multimedia applications with variable-bit-rate, mainly using VHDL and SystemC. Experimented with post-synthesis circuit optimization for leakage power minimization through gate resizing and dynamic voltage scaling (DVS).
This section lets you add any degrees or diplomas you have earned.
Politecnico di Torino
Master's degree, Computer Engineering
Jan 2019 - Jan 2021
EUR-ACE® Accredited program held in English. Embedded Systems orientation.
Universidade Federal de Santa Catarina
Bachelor's degree, Computer Engineering
Sep 2012 - Jul 2018
Thesis: Packet delivery monitoring service on Networks-on-Chip
Design and evaluation of a service for monitoring the delivery of data packets of a Network-on-Chip (NoC) in a non-intrusive architecture, i.e., collecting data traffic without interfering with the routers' operation, subsequently applying optimization techniques to improve latency.
Design and evaluation of a service for monitoring the delivery of data packets of a Network-on-Chip (NoC) in a non-intrusive architecture, i.e., collecting data traffic without interfering with the routers' operation, subsequently applying optimization techniques to improve latency.
Designing PCBs 5x Faster Despite the Pandemic
Feb 2021
Simulation-Driven Design of a Hyperloop Capsule Motor
Feb 2021
Dell Solutions for Engineering Businesses to Thrive During Remote Work
Nov 2020