Patrick Lehmann
Botzingen, Germany

Mr. Patrick Lehmann studied computer science at Technische Universität Dresden, Germany. He started to teach computer engineering and architecture as a tutor in his 3rd year. Later on he specialized in digital design, FPGA technology, and high speed communications. He shared his gained knowledge in labs, in research articles, and on social platforms. His research focuses on digital design with VHDL as well as the integration of EDA design steps into a Git and web services based development flow. Mr. Lehmann is one of developers and maintainers of The PoC-Library, a platform and vendor independent open source IP core library. He is also a contributor to the free VHDL simulator GHDL. In 2016, he started an initiative called "Open Source VHDL Group". Mr. Lehmann is active in the IEEE P1076 "VHDL Analysis and Standardization Group" since 2014. He detailed and wrote major parts of the language changes for the upcoming VHDL revision. In 2017 he became an IEEE Standards Association member and was announced vice-chair of the P1076 working group. Since June 2017, Mr. Lehmann got employed by PLC2 GmbH as a developer and trainer.

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May 2017 - Aug 2020 (3 years 3 months)
Freiburg im Breisgau, Germany
FPGA Engineer, VHDL Expert and Trainer
python3 c c# git gitlab
Technische Universität Dresden
8 years 3 months
Dresden Area, Germany
Scientific Research Assistant
Jun 2012 - Jan 2017 (4 years 7 months)
c c# python3 git github
Oct 2008 - Jun 2012 (3 years 8 months)
c c# vbnet git
Jul 2005 - Mar 2006 (8 months)
Beelitz, Germany
Private First Class
Basic military service (9 months). Basic military training at 2nd Company of the 173th Supply and Training Center (Burg near Magdeburg). Training for missions in foreign countries to prevent conflicts.
Served at technical operations group in the spare parts store at 2nd Company of the 171th Logistic Battalion (Beelitz near Berlin).
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The PoC-Library
Jan 2012 - Present
PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierarchy.

Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based front end.
Sep 2016 - Present
A streaming based VHDL parser.
Dec 2014 - Present
Providing scripts, test cases and support for the open source VHDL-2008/93/87 simulator GHDL.

This section lets you add any degrees or diplomas you have earned.
Technische Universität Dresden
Diplom-Informatiker, Informatik
Dec 2005 - Dec 2009
Technische Universität Dresden
Bachelor of Science - BSc, Computer Science
Dec 2009 - Dec 2011
Technische Universität Dresden
Master of Science - MSc, Computer Science
Dec 2011 - Dec 2015

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