Complete ASIC implementation flow which included library and cell customization, synthesis, scan insertion, DFT and ATPG, floor-planning, power distribution and analysis, low-power design and optimization, place and route optimization, clock-tree synthesis and optimization, parasitic extraction, static-timing analysis (STA), signal-integrity analysis, timing closure and signoff, ECO, physical signoff (DRC/ERC/LVS), as well as design for manufacturing (DFM) enhancements for sub-micron technology designs.
Drove the complete digital implementation and porting of Synopsys MSIPs (USB2 USB3) from prototype design and specification to testchip for silicon validation (RTL to GDSII).